IWAHPCE 2025

The IWAHPCE 2025 workshop was held in conjunction with HPC Asia 2025 in Hsinchu, Taiwan, February 19-21, 2025.

Workshop Overview

This workshop aims to provide the opportunity to share the practice and experience of high-performance computing systems using the Arm architecture and their performance and applications. The last few years have seen an explosion of 64-bit Arm-based processors targeted toward server and infrastructure workloads, often specializing in a specific domain such as HPC, cloud, and machine learning. Fujitsu’s A64FX and Marvell’s ThunderX2 have been used in several large-scale HPC systems, and Amazon’s Graviton2 has been adopted by Amazon EC2. Moreover, Amazon’s Graviton3, NVIDIA Grace CPU Superchip, and SiPearl’s Rhea system-on-chip have recently been announced or become accessible. Sharing the practice and experiences using these Arm-based processors contributes to advancing high-performance computing technology for newly designed systems using emerging Arm-based processors.

Program

Time Speaker(s) Title
09:00-09:10 Miwako Tsuji Opening Remarks
09:10-10:00 Koichi Shirahata Invited Talk: Fugaku-LLM: A Large Language Model Trained on the Supercomputer Fugaku (slides)
10:00-10:30 Shinji Sumimoto, Takashi Arakawa, Yoshio Sakaguchi, Hiroya Matsuba, Satoshi Ohshima, Hisashi Yashiro, Toshihiro Hanawa, Kengo Nakajima Accelerating Heterogeneous Coupling Computing with WaitIO Using RDMA
10:30-11:00   Break
11:00-11:30 Oscar Hernandez, Thomas Wang, Wael Elwasif, Filippo Spiga, Francesca Tartaglione, Markus Eisenbach, Ross Miller Preliminary Study on Fine-Grained Power and Energy Measurements on Grace Hopper GH200 with Open-Source Performance Tools
11:30-12:00 David Carlson, Nikolay Simakov, Rodrigo Ristow Hadlich, Anthony Curtis, Joshua Martin, Gaurav Verma, Smeet Chheda, Firat Coskun, Raul Gonzalez, Daniel Wood, Feng Zhang, Robert Harrison, Eva Siegmann The AmpereOne A192-32X in Perspective: Benchmarking a New Standard
12:00-12:30 Xuanzhengbo Ren, Yuta Kawai, Hirofumi Tomita, Seiya Nishizawa, Takahiro Katagiri, Tetsuya Hoshino, Daichi Mukunoki, Masatoshi Kawai, Toru Nagai Performance Evaluation of Loop Body Splitting for Fast Modal Filtering in SCALE-DG on A64FX

Topics

Topics of interest included:

  • HPC Applications
  • Performance Analysis, Performance Modeling & Measurement
  • SVE Vectorization analysis
  • Programming Models & System Software
  • Networking and accelerators such as GPUs
  • Artificial Intelligence and Machine Learning
  • Emerging Technologies

Important Dates

  • Full Paper Submission: 23 December 2024
  • Notification: 12 January 2025
  • Camera ready: 15 January 2025

Submission site: EasyChair IWAHPCE 2025.

Registration and Open Access Fee

  • At least one author was required to register for the conference.
  • Based on ACM’s Open Access publication policy, the publication fee was to be contacted with and collected by ACM directly from the authors.
  • If an institution was a member of the ACM Open program, the paper could be published with no charge as indicated on the ACM website.

Organizers and Program Committee

Organizer and Workshop Chair

  • Miwako Tsuji, RIKEN R-CCS
  • Eva Siegmann, Stony Brook University
  • Filippo Spiga, NVIDIA

Program Committee

  • Conrad Hillairet, Arm
  • Csaba Csoma, AWS
  • Estela Suarez, JSC
  • Eva Siegmann, Stony Brook University
  • Fabio Banchelli, BSC
  • Filippo Spiga, NVIDIA
  • Gilles Fourestey, EPFL
  • Jens Domke, RIKEN R-CCS
  • John Cazes, TACC
  • Luca Fedeli, CEA
  • Min Li, Huawei
  • Miwako Tsuji, RIKEN R-CCS
  • Tetsuya Odajima, Fujitsu
  • Wael Elwasif, ORNL
  • Yuetsu Kodama, RIKEN R-CCS